This application claims priority to Korean Patent Application No. 2002-1874, filed on Jan. 12, 2002.
1. Field of the Invention
The present invention generally relates to semiconductor memory, and more specifically, to static random access memories (SRAMs) employing twin memory cells as a storage unit.
2. Discussion of Related Art
Single-transistor dynamic random access memories are well known in the field of semiconductor memory devices. As shown in FIG. 1, a unit memory cell MC1 or MC2 comprises of one transistor TR and one capacitor C. A gate of the cell transistor TR is coupled to a wordline WL1, and a current channel of the cell transistor is formed between a bitline BL and a plate voltage terminal Vp that is connected to an electrode of the cell capacitor C. Another memory cell MC2, whose gate is coupled to another wordline WL2, forms its current channel between another bitline BLB (complementary to BL) and an electrode of the cell capacitor C. The bit line pair of BL and BLB are coupled to a sense amplifier 12.
In the structure of the DRAM cell array, if the wordline WL1 is selected, a cell data stored in the memory cell MC1 is transferred to the bitline BL through a charge sharing effect. The bitlines BL and BLB that have been held on a precharge voltage, e.g., at one half of a power supply voltage, increase/decrease or decrease/increase according to the data stored in the memory cell MC1 through the charge sharing. The voltage level of the bitline BL rises up to a high level if the data is xe2x80x9c1xe2x80x9d and falls down to a low level if the data is xe2x80x9c0xe2x80x9d. Then, the sense amplifier 12 detects and amplifies the voltage difference between the bitlines BL and BLB.
Leakage currents arising from the structural properties of the DRAM reduce the charge amount of the cell capacitor, resulting in a data loss. A refresh is needed periodically to prevent the data loss. A DRAM refresh time is determined with regarding the maximal term of maintaining data xe2x80x9c1xe2x80x9d in a memory cell. One method for achieving a low-power operation is associated with the extension of the refresh time (or refresh period). Lengthening a refresh time is possible by adopting a twin-cell structure in a memory cell array, as shown in FIGS. 2 and 3. FIGS. 2 and 3 show twin-cell arrays also applicable in SRAMs.
In FIG. 2, one twin-cell, as a SRAM cell unit, comprises two DRAM-type cells MC1 and MC2. Each cell comprises one transistor TR and one capacitor C. While the cells MC1 and MC2 are respectively connected to the bitlines BL and BLB, which are coupled to a sense amplifier 22, the cell gates are coupled to one wordline WL1 in common. The cells MC1 and MC2 store a pair of complementary data bits xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d.
Another kind of the twin-cell, as shown in FIG. 3, is a modification of the twin-cell structure of FIG. 2 in an arrangement pattern. Bitlines BL1xcx9cBL4 are alternately arranged in a column and a twin-cell is composed of two DRAM-type cells MC1 and MC2 (or MC3 and MC4) connected respectively to BL1 and BL3 (or BL2 and BL4). The bitlines BL1 and BL3, as a pair, are coupled to a sense amplifier 32, while BL2 and BL4 as another bitline pair are coupled to sense amplifier 34. A wordline WL1 is commonly coupled to gates of the cells MC1 and MC3 while a wordline WL2 to gates of MC2 and MC4. The cells in one twin-cell store a pair of complementary data bits logically.
In with a refresh of the twin-cell structure of FIG. 2, referring to FIG. 4A, the bitlines BL and BLB are set up to a precharge voltage VBL (0.5 AIVC) in response to a precharge signal PEQ before the wordline WL1 becomes active. At this time, assuming that the cell is preparing to store data xe2x80x9c1xe2x80x9d in MC1 and xe2x80x9c0xe2x80x9d in MC2, a cell node CN1 between the cell transistor and capacitor in MC1 maintains the power supply voltage level AIVC corresponding to data xe2x80x9c1xe2x80x9d while a cell node CN2 between the cell transistor and capacitor in MC2 hold a ground voltage level GND corresponding to data xe2x80x9c0xe2x80x9d. Once the wordline WL1 is active, a charge sharing starts between MC1 and BL and between MC2 and BLB. As a result, a BL voltage increases by Vcsu, the voltage difference between the bitline voltage VBL (0.5 AIVC) to a shared-in voltage supplied from the cell MC1 (CN1), while BLB voltage decreases by Vcsd the voltage difference between VBL and a shared-out voltage discharged out of the cell MC2 (CN2). With a slight estrangement between BL and BLB, the sense amplifier 22 begins developing a voltage difference and thereby the bitline BL rises up to AIVC while the counter bitline BLB falls down to a ground voltage GND. At this time, the current voltage levels on BL and BLB are restored into the cell nodes CN1 and CN2, respectively. After then, if the wordline becomes inactive, the bitlines BL and BLB are set on the precharge voltage in response to the precharge signal PEQ.
As another operational feature for the twin-cell SRAM employing a column selection line CSL, referring to FIG. 4B, the column selection line CSL becomes conductive when a voltage difference is sufficiently settled between the bitlines BL and BLB after a charge sharing therebetween. The active CSL electrically connects the bitlines BL and BLB to corresponding input/output lines. During the CSL activation, the input/output lines have a precharge voltage level of an internal power supply voltage (i.e., AIVC), and the bitline BLB and the cell node CN2 are held at a clamping level. The bitline BL and the cell node CN1 are not affected. After CSL becomes inactive, BLB and CN2 fall to GND. Restored in the cell nodes, the bitline WL1 is shut down and the bitlines BL and BLB return to the precharge voltage level VBL in response to the precharge signal PEQ.
As aforementioned, since the DRAM-type cells in the twin-cell unit store a pair of complementary data bits, a bitline voltage difference is twice as large as that of the single cell structure. As shown in FIGS. 4A and 4B, the sense amplifier (22, 32 or 34) can take the voltage differential value of 2Vcs because BL and BLB increase and decrease simultaneously, by the Vcs through the charge sharing operations.
Therefore, the twin-cell memory does not need to define a refresh cycle time or period, capable of a normal sensing operation even though a leakage current dissipate a voltage level of the cell node, holding data xe2x80x9c1xe2x80x9d, to be lower than the bitline precharge voltage VBL. Such a twin-cell memory has a longer refresh time (e.g., several seconds) than the traditional single cell memory typically about 100xcx9c200 ms. Further, a stand-by current is reduced as compared to the single cell memory. The refresh operation is similar to a normal read operation except that sense data does not turn out of the memory chip.
An instance of a SRAM-type memory, as well as DRAMs, employing the twin-cell structure has been described in the publication, entitled xe2x80x9c2Mxc3x9716 bit uni-transistor random access memoryxe2x80x9d, for Product No. xe2x80x9cK1S321615Mxe2x80x9d (May 2001), so called xe2x80x9cUtRAMxe2x80x9d. The UtRAM is constructed of the same internal structure as a traditional DRAM while using the same commands as SRAM, but conducts a refresh operation automatically by means of an internal control unit without an external refresh command. Thus, it performs a refresh operation for at least each cycle period, even during read/write commands. If the refresh operation is not performed for each cycle period, a refresh operation concurrent with read/write operations can result in loss of data stored in memory cells. As a result, the twin-cell SRAM needs to lengthen an access time or to degrade an operation speed relative to other single-cell DRAMs.
Therefore, a need exists for a system and method for a twin-cell memory device having a long refresh time and high speed of operation
It is therefore an object of the present invention to provide a twin-cell SRAM enhancing access time and speed in operation.
It is another object of the present invention to provide a method for controlling wordlines in a twin-cell SRAM with a shortened wordline activation time
It is further another object of the present invention to provide a method for conducting operations of reading, writing, and refreshing in a DRAM-type SRAM, with a shortened wordline activation time.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.